Capacitor multipler circuits and the applications thereof to attenuate row-wise temporal noise in image sensors

ABSTRACT

The various embodiments disclose capacitor multiplier circuits that may be integrated into imaging devices, such as for semiconductor Complimentary Metal Oxide Semiconductor (CMOS) image sensors, to create an effective capacitance in response to a low frequency, such as row-wise temporal noise, that may be generated along a row of image sensor pixels. The created effective capacitance from any one of the capacitor multiplier circuits along with a small signal resistance created by a trans-conductance of a current biasing transistor form a low pass filter that will attenuate the low frequency noise.

TECHNICAL FIELD

This invention relates to integrated circuitry for memory storagedevices and applications thereof and, more particularly, to capacitormultiplier circuits and capacitor multiplier circuits for imagingdevices, such as for Complimentary Metal Oxide Semiconductor (CMOS)image sensor devices.

BACKGROUND

In a typical analog CMOS fabrication process, capacitors are usuallyrealized using polysilicon-to-polysilicon layers. In this realization,two layers of polysilicon sandwich a thin silicon dioxide (SiO₂) layer.This structure usually creates a relatively high capacitance per area sothat the real estate chip area remains low and thus the cost ofrealizing the capacitor remains low. The capacitor density realized bythese two layers is in the order of a few femto-farads per square micron(fF/μm²).

However, in a typical digital CMOS fabrication process, because twolayers of polysilicon may not be available, capacitors may be realizedusing metal-to-metal layers. The capacitor density realized by two metallayers is usually even lower because the oxide between these two layersis even thicker that the polysilicon-to-polysilicon layer available inan analog CMOS process. Therefore, realizing a physically largecapacitor on the integrated circuit (IC) is very costly in anyintegrated circuit process unless special fabrication process steps havebeen added to implement it. However, fabrication process modificationmay be very costly. IC designers usually consider capacitors higher than100 pF a physically large capacitor with unreasonable fabrication costsand therefore such a large capacitor can be avoided unless there is nochoice or the benefit of having such a large capacitor outweighs itsreal-estate cost.

When considering the use of large capacitors for noise attenuation in atypical CMOS image sensor, the voltages on a floating diffusion of theimage sensor pixels are sensed by a gate of a transistor which isconfigured as a source-follower amplifier. DC bias currents insource-amplifiers of a single row are supplied by a series of currentsources. One of the sources of noise in CMOS image sensors is row-wisetemporal noise. This noise shows up as strips that change theirlocations every time a new frame of an image is captured. The strips arenot spatially fixed or stationary and their locations are a function oftime, thus the term temporal noise.

FIG. 1 depicts a simplified circuit diagram 100 comprising a row ofimage sensor pixels and their associated bias current sources 105connected between ground 101 and VAAPIX supply 102. Each image sensorpixel comprises floating diffusion photodiode 103 and source followeramplifier 104 of which are selected by row select transistor 105. Asshown in FIG. 1, the VLN line (node 106) is a single DC voltage set bydiode connected transistor M₁ 109, that supplies bias voltage to allbias current sources 107. In this layout, the VLN line 106 is usually ametal layer that extends across the image sensor pixel array from oneside of the imaging integrated circuit (IC) to the other. Depending onthe size of the CMOS image sensor, VLN line 106 can be a few millimeterslong, which is much larger than a typical layout trace. This long trace,being a relatively high impedance line, acts as an antenna in the ICthat can pick up noise from any noisy environment (digit switching,ground bounces, supply bounces, etc.).

In the CMOS image sensor, such as the image sensor 100 depicted in FIG.1, one of the mechanisms that causes a source of noise, referred to asrow-wise temporal noise, is the temporal noise developed on the VLN line106. By placing a capacitor 108 between VLN line node 106 to ground 101,it is possible to filter out (attenuate) some of the noise present onthe VLN line. However, this capacitor is required to be large due to therow-wise temporal noise frequency being in the low frequency range. Thecapacitor 108 between VLN line 106 and ground 101 and the small signalresistance created by the trans-conductance (1/gm) of the diodeconnected transistor M₁ 109, form a low pass filter that attenuates thenoise on the VLN line. The larger the capacitor, the lower the pole ofthe low-pass filter, thus producing a quieter DC bias voltage on the VLNline. To improve the row-wise temporal noise, the capacitor should be inthe range of several hundreds of pico-farad up to a few nano-farad,which presents a major fabrication obstacle in creating the large noiseattenuating capacitor needed. Due to limited space on the IC die, thephysical size of capacitor needed to attenuate the row-wise temporalnoise is prohibitive.

Therefore, what is needed in the art for integrated circuits is a way toeffectively attenuate temporal noise by providing an effective largecapacitance, which, in conjunction with other circuit elements willcreate a low pass frequency filter that may be used to reduce row-wisetemporal noise, such as in a CMOS image sensor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a prior art illustration of an image sensor circuit comprisinga row of image sensor pixels and the associated current sources.

FIG. 2 is a conceptual circuit of the present disclosure depicting anN-times capacitor multiplier circuit and its equivalent AC circuit.

FIG. 3 is an embodiment of the present disclosure depicting a capacitormultiplier circuit utilizing a simple current source that may be coupledto an image sensor circuit.

FIG. 4 is another embodiment of the present disclosure depicting a novelcapacitor multiplier circuit utilizing a cascode current source that maybe coupled to an image sensor circuit.

FIG. 5 is another embodiment of the present disclosure depicting acapacitor multiplier circuit utilizing complementary current sourcesthat may be coupled to an image sensor circuit.

FIG. 6 is another embodiment of the present disclosure depicting a novelcapacitor multiplier circuit utilizing output resistance boosted currentsources that may be coupled to an image sensor circuit.

FIG. 7 is an illustration of an AC frequency response curverepresentative of capacitor multiplier circuits of the presentdisclosure and an ideal capacitor.

FIG. 8 is an illustration of a block diagram representing any one of thecapacitor multiplier circuits of the present disclosure, butspecifically showing the integration of a capacitor multiplier circuitof FIG. 3, containing the components thereof, connected to a row of CMOSimage sensor pixels.

FIG. 9 depicts a processor system having digital circuits, which couldinclude any of the CMOS image sensor capacitor multiplier circuits ofthe present disclosure.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration of specific embodiments in which the inventionmay be practiced. These embodiments are described in sufficient detailto enable those skilled in the art to practice the invention, and it isto be understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the invention.

The term “pixel” refers to a picture element unit cell containing aphotosensor and transistors for converting electromagnetic radiation toan electrical signal.

Preferred embodiments of the present disclosure provide capacitormultiplier circuits and the integration thereof into IC devices such asfor CMOS Image sensor devices, as described below with reference toFIGS. 3-6 and general implementations thereof in FIG. 8 and FIG. 9.

FIG. 2 depicts a basic concept of a capacitor multiplier circuit 200 andits equivalent AC circuit 210. Circuit 200 is connected between supply202 (VAA) and ground 201 with DC current sources 203 and 204 supplyingcurrent source NMOS transistors 205 (M₁) and diode connected transistor206 (M₂). The aspect ratio, i.e. channel Width/Length (W/L) of currentsource NMOS transistor 205 (M₁) is N times larger than the aspect ratioof diode-connected NMOS transistor 206 (M₂). The capacitor multipliercircuit 200 realizes a large capacitance (or equivalent capacitor,C_(eff)) from a relatively small on-chip capacitor 207 (C) with the helpof a common current multiplier circuit. An equivalent capacitance 208(C_(eff)) of a capacitor multiplier circuit is a much larger capacitancefrom an AC standpoint when looking at a V_(in) terminal to ground. Thecapacitor multiplier circuit can only generate a large groundedcapacitor as it is not possible to create a fully floating capacitormultiplier. However, for the purpose of the row-wise temporal noisereduction, only a large capacitance from VLN line to ground is required.

The capacitor multiplier circuit 200 works as follows: The AC currentinput signal i_(in) derives the capacitor 207 (C) and the currentcontrolled current source or current amplifier made up of NMOStransistor 205 (MI) and diode connected NMOS transistor 206 (M₂).Assuming the DC current sources 203 (NI_(DC)) and 204 (I_(DC)) areperfect (ideal) sources, the following equations for an AC signal can bewritten as:

i _(in) =i _(c) +Ni _(c)=(N+1)i _(c),   (1)

Where in the s-domain analysis of an AC signal capacitor C is replacedby an equivalent impedance as:

C=1/sC _(eff), then   (2)

v _(in) /i _(in)=1/sC _(eff) =v _(in)/(N+1)i _(c)=1/(N+1)sC.   (3)

Therefore the effective (resulting) capacitance, as illustrated inequivalent circuit 201, will become:

C _(eff)=(N+1)C.   (4)

Equation 4 demonstrates the DC current can be easily multiplied, such asby a factor of 10 to 100. For example, if N=80, and C=25 pF, thenC_(eff)=2025 pF. It is noted that assumptions for reaching such a highcapacitance value are: 1) The DC current sources are considered to beideal, which means that their output impedance is infinite. 2) Thebottom plate of the 25 pF capacitor must be as low impedance aspossible. 3) The larger the N value, the less accurate is the currentamplification. The sizing of the NMOS and PMOS transistors (channelwidth (W) and channel length (L)) for each of the embodiments of thepresent invention will be determined by typical CMOS design rules and itis desired that the value of N be reduced as much as possible dependingon how big a capacitance is desired.

An embodiment of the present disclosure, as depicted in FIG. 3, shows acapacitor multiplier circuit 300 connected between supply 302 (VAA) andground 301 using a simple current source comprising DC current sourcePMOS transistor 303 (M3), sized as N(W/L), and PMOS transistor 304 (M₄),sized as WAL connected to current control NMOS transistor 306 (M₁),sized as N(W/L) and diode connected NMOS 307 (M₂), sized as WAL.Capacitor 308 (C) is connected in parallel to the interconnected NMOStransistors 306 and 307 and PMOS transistors 303 and 304 and isresponsive to an AC signal that generates v_(in) and i_(in). Diodeconnected PMOS transistor 305 (M₅) provides current, 309 (I_(BIAS)) toPMOS transistors 303 (M₃) and 304 (M₄) that in turn sets the DCreference current I_(DC) (from M₄) and DC output current NI_(DC) (fromM₅), as determined by the sizing of each transistor. Diode connectedNMOS transistor 307 (M₅) sets the biasing level to output NMOStransistor 306 (M₁) and the current amplification, in response to an ACis determined by the sizing of each transistor as discussed in FIG. 2.

Continuing with FIG. 3 and using the analysis of an AC signal shown inFIG. 2, the effective capacitance (C_(eff)) of capacitor 308 (C) inresponse to an AC input (v_(in)) is derived by a generated i_(in) tocreate C_(eff)=(N+1)C, thus multiplying the effective capacitance of arelatively small capacitor 308 (C). When coupling the capacitormultiplier circuit 300 to supply a row of image sensor pixels, such aspresented in FIG. 1, C_(eff) will create a desired filtering capacitancebetween VLN line 106 (seen in FIG. 1) and ground which will effectivelyfunction as a means to filter or attenuate row-wise temporal noise(i.e., low frequency noise up to 1 MHz and particularly in the range of1 KHz-1 MHz) along the row of image sensor pixels 101.

Another embodiment of the present disclosure, as depicted in FIG. 4,shows a capacitor multiplier circuit 400 connected between supply 402(VAA) and ground 401 using a PMOS cascode current source. Capacitormultiplier circuit 400 comprises an NMOS current source of NMOStransistor 409 (M₁), sized as N(W/L), and diode connected NMOS 410 (M₂),sized as W/L, connected to the cascode current source arrangement ofPMOS transistor 406 (M₆) and PMOS transistor 407 (M₇) and PMOStransistor 403 (M₃), sized as N(W/L), and PMOS transistor 404 (M₄),sized as W/L. Capacitor 411 (C) is connected in parallel to PMOStransistors 406 and 407 and NMOS transistors 409 (M₁) and 410 (M₂) andis responsive to an AC signal that generates v_(in) and i_(in).

Diode connected PMOS transistor 405 (M₅) provides DC bias current, 412(I_(BIAS1)) to PMOS transistors 403 (M₃) and 404 (M₄) and diodeconnected PMOS transistor 408 (M₈) provides DC bias current, 413(I_(BIAS2)) to PMOS transistors 406 (M₆) and 407 (M₇) that in turn setthe DC reference current I_(DC) (via M₇ and M₄) and DC output currentNI_(DC) (via M₆ and M₃) as determined by the sizing of each transistor.Diode connected NMOS transistor 410 (M₂) sets the biasing level tooutput NMOS transistor 409 (M₁) and the current amplification, inresponse to an AC single, is determined by the sizing of each transistoras discussed in FIG. 2.

Again, as discussed in FIG. 2, the effective capacitance (C_(eff)) of411 (C) in response to an AC input (v_(in)) is derived by the generatedi_(in) to create C_(eff)=(N+1)C, thus multiplying the effectivecapacitance of a relatively small capacitor 411 (C), when coupling thecapacitor multiplier circuit 400 to supply a row of image sensor pixels,such as presented in FIG. 1. C_(eff) of FIG. 4 will create a desiredfiltering capacitance between VLN line 106 (seen in FIG. 1) and groundwhich will effectively function as a means to filter row-wise temporalnoise (i.e., low frequency noise up to 1 MHz), particularly in afrequency range of 1 KHz to 1 MHz as illustrated in the frequencyresponse curve of FIG. 7 (discussed later).

Another embodiment of the present disclosure, as depicted in FIG. 5,shows a capacitor multiplier circuit 500 connected between supply 502(VAA) and ground 501 using complementary current sources. The firstcomplementary current source provides DC current 510 (I_(DC)), as set bydiode connected NMOS transistor 506 (M₂), sized as W/L, and currentamplifier NMOS transistor 505 (M₁), sized as N(W/L), with capacitor 509(C₂) connected in parallel across NMOS transistors 505 (M₁) and 506(M₂). In a similar, but complimentary manner, the second complementarycurrent source provides bias current 508 (I_(DC)) as set by diodeconnected PMOS transistor 504 (M₄), sized as W/L, and current amplifierPMOS transistor 503 (M₃), sized as N(W/L), with capacitor 507 (C₁)connected in parallel across PMOS transistors 503 (M₃) and 504 (M₄).

The capacitance values of C₁ and C₂ of FIG. 5, when compared to thecapacitor multiplier circuits having a single capacitor (C), will behalf the capacitance of C and thus represented as C₁=C/2 and C₂=C/2.Thus, in the capacitor multiplier circuit of FIG. 5, capacitors 509 (C₂)and 507 (C₁) may be even smaller in physical size as C_(eff) will resultin the parallel combination of these two capacitors, as the effectivecapacitance (C_(eff)) of capacitor 509 (C₂) plus capacitor 507 (C₁) inresponse to an AC input (v_(in)) is derived by the generated i_(in) tocreate C_(eff)=(N+1)(C₁+C₂) or C_(eff)=(N+1)(C/2+C/2)=(N+1)C. Thus, theeffective capacitance results in the multiplying of two relatively smallcapacitors 509 and 507, when coupling the capacitor multiplier circuit500 to supply a row of image sensor pixels, such as presented in FIG. 1.C_(eff) of FIG. 5 will create a desired filtering capacitance betweenVLN line 106 (seen in FIG. 1) and ground and will effectively functionas a means to filter row-wise temporal noise (i.e., low frequency noiseup to 1 MHz), particularly in a frequency range of 1 KHz to 1 MHz asillustrated in the frequency response curve of FIG. 7.

Another embodiment of the present disclosure, as depicted in FIG. 6,shows a capacitor multiplier circuit 600 connected between supply 602(VAA) and ground 601 using output resistance boosted current sources.The first output resistance boosted current source comprises NMOStransistor 606 (M₁), sized as N(W/L), diode connected NMOS 607 (M₂),sized as W/L, that sets bias current 614 (I_(DC)) and is connected tooperational amplifier 610 (A₂) which drives NMOS transistor 608 (M₃),sized as N(W/L). Capacitor 612 (C₂) is connected in parallel to thefirst output resistance boosted current source by connecting across thedrains of NMOS transistor 608 (M₃) and NMOS transistor 607 (M₂). Thesecond output resistance boosted current source comprises PMOStransistor 603 (M₄), sized as N(W/L), diode connected PMOS 604 (M₅),sized as W/L, that sets bias current 613 (I_(DC)) and is connected tooperational amplifier 609 (A₁) that drives PMOS transistor 605 (M₆),sized as N(W/L). Capacitor 611 (C₁) is connected in parallel to thesecond output resistance boosted current source by connecting across thedrains of PMOS transistor 605 (M₆) and PMOS transistor 604 (M₅).

As discussed in FIG. 5, the capacitance values of C₁ and C₂ of FIG. 6,when compared to a capacitor multiplier circuit having a singlecapacitor (C), will be half the capacitance of C and thus represented asC₁=C/2 and C₂=C/2. Thus, in the capacitor multiplier circuit of FIG. 6,capacitors 611 and 612 may be even smaller in size as the C_(eff) willbe result in the parallel combination of these two capacitors, as theeffective capacitance (C_(eff)) of capacitor 612 (C₂) plus capacitor 611(C₁) in response to an AC input (v_(in)) is derived by the generatedi_(in) to create C_(eff)=(N+1)C or C_(eff)=(N+1)(C/2+C/2)=(N+1)C. Thusthe effective capacitance results in the multiplying of two relativelysmall capacitors 612 and 611, when coupling the capacitor multipliercircuit 600 to supply a row of image sensor pixels, such as presented inFIG. 1. C_(eff) of FIG. 6 will create a desired filtering capacitancebetween VLN line 106 (seen in FIG. 1) and ground and will effectivelyfunction as a means to filter row-wise temporal noise (i.e., lowfrequency noise up to 1 MHz), particularly in a frequency range of 1 KHzto 1 MHz.

The frequency response curves of FIG. 7 plotted as 1/ωC (magnitude ofimpedance) vs. frequency (Hz), shows the frequency responses of thecapacitor multiplier circuit arrangements of FIG. 4 (curve 702) and FIG.5 (curve 703), each of which are compared against curve 701 of an ideal2025 pF capacitor. As shown in FIG. 7 both circuit configurations have asimilar frequency response. At low frequencies (below 1 KHz) and at highfrequencies (above 1 MHz), both circuit arrangements deviate from anideal 2025 pF capacitor response as frequency response curves 702 and703 begin to flatten out above and below those frequency ranges.However, in the frequency range of approximately 1 KHz to 1 MHz, bothcapacitor multiplier circuit arrangements of FIG. 4 and FIG. 5 actalmost identical to the response of an ideal capacitor.

It is anticipated that other values of derived effective capacitancesfrom capacitor multiplier circuits, such as the circuits of FIG. 3 andFIG. 6, will have similar frequency response results to those asdepicted in the frequency response curve of FIG. 7, when compared to therespective ideal capacitor. It is further anticipated that frequencyresponse of the capacitor multiplier circuit of FIG. 6 will provide thebest frequency response of the several embodiments of capacitormultipliers circuits disclosed when compared to an ideal capacitor dueto the enhanced output impedance. However, due to being a somewhatcomplicated circuit, this circuit may possess possible fabricationlimitations when integrated into a CMOS Image sensor device. However,the capacitor multiplier circuit of FIG. 6 may prove to serve as asuperior capacitance multiplier in many integrated circuit applications,such as analog devices that would benefit from a small signal capacitormultiplier circuit for attenuating low frequencies.

The following example is used to estimate the range of the row-wisetemporal noise frequency for a typical image sensor case. If the framerate of a typical CMOS image sensor is 10 frames per second and thesensor has approximately 2500 rows per frame then the row-wise temporalnoise frequency must be in the vicinity of 25 KHz. Thus it can beassumed the row-wise temporal noise frequency is in the range of a fewtens of KHz, which is a slow varying noise. At around this frequencyrange, as demonstrated in the frequency response curve of FIG. 7, thecapacitor multiplier AC response is identical to the performance of anideal 2025 pF capacitor. Therefore, the various capacitor multipliercircuits of the present disclosure can be utilized to mimic a very largecapacitor on chip (integrated circuit), such as on an image sensor chipto act as a very large capacitance (in the order of 2 nF) in order tofilter out the temporal row-wise noise on the VLN line.

The capacitor multiplier is a small, simple, stand alone circuit thatcan easily be realized on-chip by one skilled in the art and can beenabled and disabled by turning on/off the DC current sources that feedthe circuit. The block diagram of FIG. 8 represents an implementation ofany one of the capacitor multiplier circuits of the present disclosureas integrated into a CMOS image sensor device 800. As an example, thecapacitor multiplier circuit of FIG. 3 is integrated with an imagesensor circuit comprising a row of image sensor pixels and theirassociated current sources. It is to be understood that any of thecapacitor multiplier circuits disclosed, including any similar designsthereof, can be integrated with an image sensor circuit in the mannerindicated with the example of FIG. 3 as subsequently set forth.

Referring now to FIG. 8, the block diagram shows CMOS image sensordevice 800 comprising an image sensor circuit 810 and a capacitormultiplier circuit 820 connected between VAAPIX 802 and ground 801. Theimage sensor circuit 810 comprises an array of image sensor pixels 840,each of which comprises a reset transistor 841, a transfer transistor842, a photodiode 843, a floating diffusion 846, a source followertransistor 844 and a row select transistor 845, connected in typicalfashion of a four transistor image sensor pixel. A row of bias currentsources 814 connect to their respective pixels 840 via the appropriaterow select transistor 845. Bias current sources 814 receive a set biasvoltage through diode connected transistor 813, which also determinesthe DC current level indicated by I_(DC) 812.

The capacitor multiplier circuit 820 comprises a simple current sourceconnected between supply 802 (VAAPIX) and ground 801 using a simplecurrent source comprising DC current source PMOS transistor 823 (M3),sized as N(W/L), and PMOS transistor 824 (M₄), sized as W/L, connectedto current control NMOS transistor 826 (M₁), sized as N(W/L) and diodeconnected NMOS 827 (M₂), sized as W/L. Capacitor 828 (C) is connected inparallel to the interconnected NMOS transistors 826 and 827 and PMOStransistors 823 and 824 and is responsive to an AC signal that generatesV_(in) and i_(in). Diode connected PMOS transistor 825 (M₅) providescurrent, 829 (I_(BIAS)) to PMOS transistors 823 (M₃) and 824 (M₄) thatin turn sets the DC reference current I_(DC) (from M₄) and DC outputcurrent NI_(DC) (from M₃) as determined by the sizing of eachtransistor. Diode connected NMOS transistor 827 (M_(s)) sets the biasinglevel to output NMOS transistor 826 (M₁) and the current amplification,in response to an AC signal, is determined by the sizing of eachtransistor as discussed in accordance with FIG. 2.

A capacitor 828 (C), in response to an AC input (v_(in)), is derived bya generated i_(in) to create C_(eff)=(N+1)C, thus multiplying theeffective capacitance of a relatively small capacitor 828 (C). With thecapacitor multiplier circuit 820 coupled to supply a row of image sensorpixels, such as image sensor pixel 840 by way of their respective biascurrent sources 807, C_(eff) will create a desired capacitance, fromfiltering capacitor 828, between VLN line 811 and ground thateffectively functions as a means to filter or attenuate row-wisetemporal noise (i.e., low frequency noise up to 1 MHz and particularlyin the range of 1 KHz-1 MHz) along the row of image sensor pixels 840.

FIG. 9 depicts a processor system having digital circuits, which couldinclude any of the CMOS image sensor cell designs of the presentdisclosure. Referring to FIG. 9, a processor system 900, such as acomputer system, generally comprises a central processing unit (CPU)901, for example, a microprocessor that communicates with aninput/output (I/O) device 906 over a bus 904. The CMOS image sensordevice 905 also communicates with the system over bus 904. The processorsystem 900 may also include random access memory (RAM) 907, and, in thecase of a computer system, may include peripheral devices such as aflash memory card 902, or a compact disk (CD) ROM drive 903 which alsocommunicate with CPU 901 over the bus 904. It may also be desirable tointegrate the CPU 901, CMOS image sensor device 905 and memory 907 on asingle IC chip. Without being limiting, such a processor system couldinclude a computer system, camera system, scanner, machine vision,vehicle navigation, video phone, surveillance system, auto focus system,star tracker system, motion detection system, image stabilization systemand data compression system for high-definition television, all of whichcan utilize the invention.

It should be noted that although the present disclosure has beendescribed with specific reference to several capacitor multipliercircuits and to CMOS image sensors comprising any one of the capacitormultiplier circuits, the invention has broader applicability and may beused in any imaging apparatus where low frequency noise, such asrow-wise temporal noise, is a concern. The above description anddrawings illustrate preferred embodiments which achieve the objects,features and advantages of the invention. It is not intended that thepresent disclosure be limited to the illustrated embodiments and anymodification thereof which comes within the spirit and scope of thefollowing claims should be considered part of the present disclosure.

1. An image sensor circuit comprising: a capacitor multiplier circuitresponsive to an alternating current signal, the capacitor multipliercircuit having a current controlled current source and a capacitor. 2.The image sensor circuit of claim 1, wherein, the capacitor multipliercircuit electrically creates an effective capacitance in response to thealternating current signal that attenuates frequencies at around 1 MHzand below.
 3. The image sensor circuit of claim 1, wherein the capacitormultiplier circuit comprises a capacitor connected across a currentsource such that the effective capacitance is created in response to anAC signal.
 4. The image sensor circuit of claim 1, wherein the AC signalcomprises row-wise temporal noise generated on the DC bias voltage lineconnecting to a row of image sensor pixels.
 5. The image sensor circuitof claim 1, wherein the capacitor multiplier circuit creates a low passfilter to frequencies between 1 KHz and 1 MHz.
 6. The image sensorcircuit of claim 3, wherein the capacitor multiplier circuit creates alow pass filter to the row-wise temporal noise along a row of CMOS imagesensor pixels, the row-wise temporal noise frequencies being between 1KHz and 1 MHz.
 7. The image sensor circuit of claim 3, wherein thecurrent source comprises a DC current source connecting to a currentcontrol current source, the capacitor connecting in parallel to both theDC current source and the current control current source.
 8. The imagesensor circuit of claim 4, wherein the DC current source comprises PMOStransistors and the current controlled current source comprises NMOStransistors.
 9. The image sensor circuit of claim 7, wherein the DCcurrent source comprises PMOS transistors arranged as a cascode currentsource.
 10. The image sensor circuit of claim 3, wherein the currentsource comprises complementary current sources, a first capacitorconnecting in parallel to a PMOS current source and a second capacitorconnecting in parallel to an NMOS current source.
 11. The image sensorcircuit of claim 3, wherein the current source comprises outputresistance boosted current sources, a first capacitor connecting acrossa PMOS current source and PMOS transistor driven by a first operationalamplifier and a second capacitor connecting across an NMOS currentsource and NMOS transistor driven by a first operational amplifier. 12.A CMOS image sensor device comprising: an image sensor circuit connectedbetween a first power supply and a second power supply; an array ofimage sensor pixel circuits, each image sensor pixel being connected toa bias current source transistor by a row select transistor, the biascurrent source transistor having a voltage bias level set by a diodeconnected transistor; a capacitor multiplier circuit being connectedbetween the first power supply and the second power supply, the outputof the capacitor multiplier circuit being connected to the diodeconnected transistor and bias current transistors, the capacitormultiplier circuit, the capacitor multiplier circuit being responsive toan alternating current signal, the capacitor multiplier circuit having acurrent controlled current source and a capacitor.
 13. The image sensorcircuit of claim 12, wherein, the capacitor multiplier circuitelectrically creates an effective capacitance in response to thealternating current signal that attenuates frequencies at around 1 MHzand below.
 14. The CMOS image sensor device of claim 12, wherein thecapacitor multiplier circuit comprises a capacitor connected across acurrent source such that the effective capacitance is created inresponse to an AC signal.
 15. The CMOS image sensor device of claim 12,wherein the AC signal comprises row-wise temporal noise generated on theDC bias voltage line connecting to a row of image sensor pixels.
 16. TheCMOS image sensor device of claim 12, wherein the capacitor multipliercircuit creates a low pass filter to frequencies between 1 KHz and 1MHz.
 17. The image sensor circuit of claim 15, wherein the capacitormultiplier circuit creates a low pass filter to the row-wise temporalnoise along a row of CMOS image sensor pixels, the row-wise temporalnoise frequencies being between 1 KHz and 1 MHz.
 18. The CMOS imagesensor device of claim 14, wherein the current source comprises a DCcurrent source connecting to a current control current source, thecapacitor connecting in parallel to both the DC current source and thecurrent control current source.
 19. The CMOS image sensor device ofclaim 15, wherein the DC current source comprises PMOS transistors andthe current controlled current source comprises NMOS transistors. 20.The CMOS image sensor device of claim 18, wherein the DC current sourcecomprises PMOS transistors arranged as a cascode current source.
 21. TheCMOS image sensor device of claim 14, wherein the current sourcecomprises complementary current sources, a first capacitor connecting inparallel to a PMOS current source and a second capacitor connecting inparallel to an NMOS current source.
 22. The CMOS image sensor device ofclaim 14, wherein the current source comprises output resistance boostedcurrent sources, a first capacitor connecting across a PMOS currentsource and PMOS transistor driven by a first operational amplifier and asecond capacitor connecting across an NMOS current source and NMOStransistor driven by a second operational amplifier.
 23. A capacitormultiplier circuit comprising: a cascode current source connectedbetween a first supply and a second supply; a capacitor connected inparallel across the cascade current source; the cascode current sourcecomprising: an NMOS current source comprising a first NMOS transistor,sized as N(W/L), and diode connected NMOS transistor, sized as W/L,connected to a cascode current source arrangement of PMOS transistorscomprising a first PMOS transistor and a second PMOS transistor, bothsized as N(W/L), and third PMOS transistor, sized as W/L; where; N=aconstant, W=a width of a channel of a field effect transistor device,and L=a length of a field effect transistor device.
 24. A capacitormultiplier circuit comprising: a complimentary pair of output resistanceboosted current sources connected between a first supply and a secondsupply; first and second capacitor connected in parallel across thecomplimentary pair of output resistance boosted current sources; thecomplimentary pair of output resistance boosted current sourcescomprising: a first output resistance boosted current source comprisinga first NMOS transistor, sized as N(W/L), and connected to a diodeconnected NMOS, sized as W/L, both of which are connected to a firstoperational amplifier that drives a third NMOS transistor sized asN(W/L); a second output resistance boosted current source comprising afirst PMOS transistor, sized as N(W/L), and connected to a diodeconnected PMOS transistor, sized as W/L, both of which are and connectedto a second operational amplifier that drives a third PMOS transistor,sized as N(W/L); where; N=a constant, W=a width of a channel of a fieldeffect transistor device, and L=a length of a field effect transistordevice.
 25. A capacitor multiplier circuit of claim 24 wherein the firstcapacitor is connected in parallel to the first output resistanceboosted current source by connecting across a drain of the second NMOStransistor and the drain of diode connected NMOS transistor.
 26. Acapacitor multiplier circuit of claim 24 wherein the second capacitor isconnected in parallel to the second output resistance boosted currentsource by connecting across a drain of the second PMOS transistor andthe drain of diode connected PMOS transistor.
 27. A processor systemcomprising: a processor, a CMOS image sensor circuit, the CMOS imagesensor circuit comprising: a capacitor multiplier circuit responsive toan alternating current signal, the capacitor multiplier circuit having acurrent controlled current source and a capacitor, the capacitormultiplier circuit supplying a bias current to an image sensor pixel.28. The image sensor circuit of claim 27, wherein, the capacitormultiplier circuit electrically creates an effective capacitance inresponse to the alternating current signal that attenuates frequenciesat around 1 MHz and below.
 29. The processor system of claim 27, whereinthe capacitor multiplier circuit comprises a capacitor connected acrossa current source such that the effective capacitance is created inresponse to an AC signal.
 30. The processor system of claim 27, whereinthe AC signal comprises row-wise temporal noise generated on the DC biasvoltage line connecting to a row of image sensor pixels.
 31. Theprocessor system of claim 27, wherein the capacitor multiplier circuitcreates a low pass filter to frequencies between 1 KHz and 1 MHz. 32.The processor system of claim 30, wherein the capacitor multipliercircuit creates a low pass filter to the row-wise temporal noise along arow of CMOS image sensor pixels, the row-wise temporal noise frequenciesbeing between 1 KHz and 1 MHz.
 33. The processor system of claim 29,wherein the current source comprises a DC current source connecting to acurrent control current source, the capacitor connecting in parallel toboth the DC current source and the current control current source. 34.The processor system of claim 30, wherein the DC current sourcecomprises PMOS transistors and the current controlled current sourcecomprises NMOS transistors.
 35. The processor system of claim 33,wherein the DC current source comprises PMOS transistors arranged as acascode current source.
 36. The processor system of claim 29, whereinthe current source comprises complementary current sources, a firstcapacitor connecting in parallel to a PMOS current source and a secondcapacitor connecting in parallel to an NMOS current source.
 37. Theprocessor system of claim 29, wherein the current source comprisesoutput resistance boosted current sources, a first capacitor connectingacross a PMOS current source and PMOS transistor driven by a firstoperational amplifier and a second capacitor connecting across an NMOScurrent source and NMOS transistor driven by a second operationalamplifier.